Development of innovative cascaded multilevel inverter topologies and switching strategies

Abstract

DC to AC conversion is an area of research which is always evolving and challenging. This research work focuses on one type of DC to AC converter, i.e., A Multilevel Inverter (MLI). The cascaded MLI is used in AC drive speed control, Electric Vehicles, DC power source utilization (such as electricity obtained from fuel cells, batteries, solar panels) and renewable energy source based power generation. The principal objective of this research work is to design the basic unit for a cascaded MLI with fewer switches that are in active conduction state in all the modes of operation irrespective of the number of output voltage levels of the inverter, which results in optimum conduction losses in the MLI. Irrespective of the switching condition, the driver circuits associated with the power switches in the MLI consumes considerable power; consequently, the design objective of an MLI is to have a fewer number of driver circuits. The driver circuit is mainly dependent on the number of power switches used in the MLI. Hence designing the MLI with less device count will result in less power consumption in the driver circuit section. An Enhanced H Bridge topology is proposed as a part of this research work. The developed basic unit has less device count, fewer switches in active conduction state in all the modes of operation irrespective of the number of output voltage levels of the inverter and hence reduced conduction losses. The device count, number of output voltage levels, number of switches that are in active conduction state in all the modes of operation, total blocking voltage of the power switches of the MLI, and design equations of the proposed topology have been compared with the existing Symmetrical and Asymmetrical (Binary and Trinary) Cascade H Bridge, Switched Series Parallel Network cascaded with two H Bridges, T-Type H Bridge and Developed H Bridge (Babaei et al.2014) topologies. The simulation was carried out for all the topologies to validate the design using MATLAB/Simulink.