Certain investigations on low power circuits and performance improvement using modified efficient charge recovery logic

dc.contributor.guideMohanbabu, G
dc.coverage.spatialCertain investigations on low power circuits and performance improvement using modified efficient charge recovery logic
dc.creator.researcherDhilipkumar, P
dc.date.accessioned2024-02-19T06:41:21Z
dc.date.available2024-02-19T06:41:21Z
dc.date.awarded2023
dc.date.completed2023
dc.date.registered
dc.description.abstractPower consumption is a critical consideration in the design of newlineVery Large-Scale Integration (VLSI) technology. The growing demand for newlinebattery-powered portable devices and Internet of Things devices has highlighted newlinethe need for low power circuits. Energy efficiency is particularly crucial in newlineportable devices that require continuous operation. Furthermore, cooling newlineequipment is expensive and can be a significant constraint in terms of power newlineconsumption. As a result, there is a need to develop new low power techniques newlinefor designing logic circuits that can operate efficiently under these constraints. newlineSuch techniques can help to ensure extended battery life and optimal newlineperformance in portable and Internet of Things devices. newlineAdiabatic logic is well known energy recovery logic among newlinethe different logic styles where it reuses the energy for low power dissipation. newlineThe energy is sent back to the power supply to reduce a power dissipation. newlineThis word Adiabatic Logic is used to define the switching circuits that can be newlineworking without losses, and the word Semi Adiabatic circuits is used to denote newlinethe switching circuits that works with a power lower than that of traditional newlineComplementary Metal Oxide Semiconductor (CMOS). In both approaches, the newlineword is used to mention that these circuits are capable of working with newlinesignificantly loser power dissipation than CMOS circuits. In this work, a new newlinedesign of adiabatic circuit, called Modified Efficient Charge Recovery Logic newline(MECRL) is proposed. To achieve minimum energy consumption, this work newlineproposes a technique in which P-MOS is added whose gate is controlled by the newlinepower clocks. By using this technique non adiabatic loss is eliminated. newline
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions21cm.
dc.format.extentxv,120p.
dc.identifier.urihttp://hdl.handle.net/10603/545890
dc.languageEnglish
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.relationp.108-119
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Information Systems
dc.subject.keywordEngineering and Technology
dc.subject.keywordInternet of Things devices
dc.subject.keywordPower consumption
dc.subject.keywordVery Large-Scale Integration
dc.titleCertain investigations on low power circuits and performance improvement using modified efficient charge recovery logic
dc.title.alternative
dc.type.degreePh.D.

Files

Original bundle

Now showing 1 - 5 of 13
Loading...
Thumbnail Image
Name:
01_title.pdf
Size:
86.56 KB
Format:
Adobe Portable Document Format
Description:
Attached File
Loading...
Thumbnail Image
Name:
02_prelim pages.pdf
Size:
1.77 MB
Format:
Adobe Portable Document Format
Loading...
Thumbnail Image
Name:
03_content.pdf
Size:
98.48 KB
Format:
Adobe Portable Document Format
Loading...
Thumbnail Image
Name:
04_abstract.pdf
Size:
95.76 KB
Format:
Adobe Portable Document Format
Loading...
Thumbnail Image
Name:
05_chapter1.pdf
Size:
311.08 KB
Format:
Adobe Portable Document Format

License bundle

Now showing 1 - 1 of 1
Loading...
Thumbnail Image
Name:
license.txt
Size:
1.79 KB
Format:
Plain Text
Description: