Performance evaluation of energy efficient adders in programmable truncated multiply and accumulate architectures

dc.contributor.guide	M, Vijayaraj
dc.coverage.spatial	Information and Communication Engineering
dc.creator.researcher	E, John Alex
dc.date.accessioned	2019-03-19T10:39:21Z
dc.date.available	2019-03-19T10:39:21Z
dc.date.awarded	n.d.
dc.date.completed	2018
dc.date.registered	n.d.
dc.description.abstract	Abstract available
dc.description.note	Data not available
dc.format.accompanyingmaterial	None
dc.format.dimensions	30cm.
dc.format.extent	xxv, 161p.
dc.identifier.uri	http://hdl.handle.net/10603/232956
dc.language	Others
dc.publisher.institution	Faculty of Information and Communication Engineering
dc.publisher.place	Chennai
dc.publisher.university	Anna University
dc.relation	151-160
dc.rights	university
dc.source.university	University
dc.subject.keyword	AccumulatorCircuit
dc.subject.keyword	Architectures
dc.subject.keyword	DynamicPower
dc.subject.keyword	SignalProcessors
dc.subject.keyword	SleepMode
dc.title	Performance evaluation of energy efficient adders in programmable truncated multiply and accumulate architectures
dc.title.alternative
dc.type.degree	Ph.D.