Improving energy efficiency through configurable system on chip block matching architectures for motion estimation in video encoding

Abstract

The emergence of large amount of data intensive multimedia applications increases the demand for computing power. The portable handheld newlinedevices must be capable of meeting these applications ever increasing newlinecomputational complexity with the available power. This led to the newlinedevelopment of flexible domain-specific coarse - grained reconfigurable newlineSystem-on-Chip designs that can identify computationally complex and newlineindependent functions with as little data dependency as possible. The combined newlineutilization of software programmability by a general purpose processor and the newlinehardware flexibility of a reconfigurable architecture is the best choice for such newlinedesigns to achieve the energy efficiency for computationally intensive newlineapplications. In multimedia processing, video compression is one of the most newlinecomputationally intensive applications. Motion estimation is the critical task in newlinevideo compression as it consumes large amount of computational time for newlinefinding the best block match by calculating Sum of Absolute Difference (SAD) newlineof different blocks in successive video frames. To overcome this problem, its newlineinherent parallel execution nature is analyzed and mapped into customized newlineparallel reconfigurable architecture to effectively manage the power and newlineresource utilization. newline newline