Investigation of different RFET devices and design of planar RFET based SRAM with soft error performance

Abstract

Various device concepts and different device structures are proposed to tackle the short channel effects faced by the bulk planar CMOS technology. Tunnel FET and junctionless FET are examples for the former. FinFET, Trigate and nanowire are the examples for the latter. Reconfigurable FET (RFET) is a new device concept evolved from Schottky Barrier MOSFET (SB MOSFET) which uses Schottky barrier tunneling. Both SBMOSFET and RFET use Silicide source-drain regions instead of heavily doped semiconductor regions. But RFET uses two gates namely, control gate and program gate. RFET achieves both P and N operations from the same device, using an extra gate called program gate. RFET concept can be combined with the multigate structures to produce multigate RFET devices. One of the chapters of this thesis analyses four different RFET structures, and in particular Silicon nanotube based RFET is analyzed in detail. ON current (ION), OFF current (IOFF), and unit gain cut-off frequency (fT) are used for this analysis. Following this, planar RFET based 6T SRAM operation is demonstrated and analyzed. The analysis includes both static and dynamic stability. READ, WRITE and HOLD Static Noise Margins (SNM), and Single Event Upset (SEU) are analyzed under this category. SEU is characterized using the minimum amount of radiation dose to flip the content of the SRAM cell, known as threshold Linear Energy Transfer (LETTH). newline