An improved system for power efficient embedded applications

Abstract

Embedded systems are found in many devices in common use today. Over the two decades, embedded processing has become ubiquitous in all forms of electronic devices so that it can provide sophisticated features and rich user experience. Along with other design parameters such as area, testability, and safety power consumption in embedded systems is considered newlineto be an important design metrics. With the tremendous growth in the usage of embedded devices, there is a strong trend towards developing battery powered wireless portable embedded systems that have to operate under stringent energy constraints. Therefore, low power consumption has emerged as an important criterion for embedded microprocessor design. There are many different low power design directions which have their own interesting set of problems to solve, like circuit-level design, CPU architectural level design, memory design, interconnection network modifications, and software design. Many times, these elements of design are orthogonal, and a combination of such solutions can be selected to suit the application to operate at very low power levels. The low power design directions in the architectural modification spread along the lines of register file structure modification, memory and cache configuration modification, instruction set compression and optimisation, power-optimised No-Instruction-Set-Computers (NISC), Application-Specific Instruction-set Processors (ASIP), data and instruction layout compiler optimisations, layered memory structure and dynamic voltage and frequency scaling newline newline