DFT Techniques for Asynchronous Dominant SoC

Abstract

Future of VLSI design is asynchronous style, owing to advantages it gives over newlinesynchronous designs. Asynchronous circuits consume less power, generate less noise, and newlineproduce less electro-magnetic interference (EMI), compared to their synchronous counterparts, newlinewithout degrading performance. Furthermore, delay-insensitive (DI) asynchronous paradigms newlinehave a number of additional advantages, especially when designing complex circuits, like newlineSystems-on-a-Chip (SoCs), including substantially reduced crosstalk between analog and digital newlinecircuits, ease of integrating multi-rate circuits, and component reuse. Asynchronous circuits can newlineutilize a synchronous wrapper, such that the end user is oblivious of the fact that the internal newlinecircuitry is actually asynchronous in nature. To meet ever demanding customers needs most of newlinethe System on chip (SoC) designs are complex in terms of functionality, performance and newlineintegration and are based on synchronous implementation. As SoC complexity increases, major newlinepower consumption is due to unnecessary switching of the clock. Other issues related to clock in newlinethe synchronous SoC design are routing, interconnection and clock skew which are complex to newlineaddress today. To tackle issues of power consumptions and clock, many researchers, newlineacademicians and design houses are working to bring the asynchronous design to fore front newlineresulting in Asynchronous dominant SoC [A-SoC]. Any new design style will not be accepted newlineuntil design methodology is proven to be efficient and compatibility with many other design newlinerelated processes such as Automated Electronic Design Automation (EDA) tools support and newlineability for radical shift in design methodology by the design houses. newlineCritical design advantage related to asynchronous design style is hazard-free newlinecommunication across the chip. But, high-concurrency in design makes them difficult to test and newlineverify. Lack of test methods and EDA Tools to complete design flow compounds testability newlineissue as most of the available commercial EDA tools are