Certain investigations on test data reduction using run length coding in benchmark circuits

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dc.contributor.guideKarthikeyan S
dc.coverage.spatialCertain investigations on test data reduction using run length coding in benchmark circuits
dc.creator.researcherThilagavathi P
dc.date.accessioned2024-09-30T06:22:19Z
dc.date.available2024-09-30T06:22:19Z
dc.date.awarded2024
dc.date.completed2024
dc.date.registered
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions21cm
dc.format.extentxvii,138p.
dc.identifier.urihttp://hdl.handle.net/10603/592603
dc.languageEnglish
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.relationp.126-137
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordAutomatic Test Equipment
dc.subject.keywordIntellectual Property
dc.subject.keywordSystem-on-Chip
dc.titleCertain investigations on test data reduction using run length coding in benchmark circuits
dc.title.alternative
dc.type.degreePh.D.

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