An algorithmic approach for optimizing page fault to increase processor performance along with thread level speculation

dc.contributor.guide	Sheena Mathew
dc.coverage.spatial
dc.creator.researcher	Jisha P. Abraham
dc.date.accessioned	2019-03-14T11:21:19Z
dc.date.available	2019-03-14T11:21:19Z
dc.date.awarded	20/12/2018
dc.date.completed	2017
dc.date.registered	10/10/2012
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	178 p.
dc.identifier.uri	http://hdl.handle.net/10603/231904
dc.language	English
dc.publisher.institution	Department of Computer Science
dc.publisher.place	Cochin
dc.publisher.university	Cochin University of Science and Technology
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering and Technology,Computer Science,Computer Science Theory and Methods
dc.title	An algorithmic approach for optimizing page fault to increase processor performance along with thread level speculation
dc.title.alternative
dc.type.degree	Ph.D.