Investigation on topologies and control of reduced switch count multilevel inverters for various applications

dc.contributor.guide	D Ramakrishna Reddy
dc.coverage.spatial
dc.creator.researcher	Rumana Abideen
dc.date.accessioned	2025-12-29T09:14:55Z
dc.date.available	2025-12-29T09:14:55Z
dc.date.awarded	2025
dc.date.completed	2025
dc.date.registered	2021
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent
dc.identifier.researcherid
dc.identifier.uri	http://hdl.handle.net/10603/684631
dc.language	English
dc.publisher.institution	Electrical and Electronics Engineering
dc.publisher.place	Hanamkonda
dc.publisher.university	Chaitanya University, Hanamkonda
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Investigation on topologies and control of reduced switch count multilevel inverters for various applications
dc.title.alternative
dc.type.degree	Ph.D.