Studies on Hybrid Static Segmentation Based Imprecise Multiplier Designs for Image Processing Applications

Abstract

newline ABSTRACT newlineApproximate computing (AC) is a transpiring trend in several digital designs, newlinealleviating the requisites of precise computation, to obtain valuable performance newlinerefinement in terms of power, speed and area. This perspective is befitting more and newlinemore important for embedded and mobile systems, characterized by severe constraints newlineof energy and speed. Moreover, approximate computing can be bounteously newlineapplicable in multiple error-resilient applications like multimedia processing, machine newlinelearning, data mining and recognition. Further with approximate computing, greater newlinespeed applications of multimedia have also provided a way for the completely new newlinearea of zenith-speed error-tolerant circuits. These implementations dispatch high newlineperformance at the cost of shrink inexactness and also such enactments reduce the newlineentanglement of the system architecture, delay and power consumption. newlineIn general, multipliers are considered to be one of the primary sub systems for newlinemicroprocessors, digital signal processors, and embedded systems with requisitions newlinefluctuating from simple filtering to convolutional neural networks (CNN). Also, they newlineplay a crucial role in DSP applications, namely in arithmetic operations. But it is newlineunfortunate that, multipliers are characterized by tricky design logics and holds one of newlinethe prominent energy-consuming digital units. Consequently, inexact multiplier newlineconfigurations have become a pivotal investigation concern in present generation. newlineNeoteric developments in the processor models are focused on the multiplier newlinearchitectures which consume minimal power at circuit level. But such architectures newlineand algorithms mostly perform their elemental operation as matrix multiplications, newlineapart from the multiplier being typically an energy-consuming integrant. In any newlinedesign, the main criteria of interest are to obtain high speed, low delay, usage of newlineminimal area and low power consumption. The duo significant, as yet often clashing newlinedesign parameters are consumption of power and speed. By ca