Modeling deep submicron MOS transistor for ultra low-power analog and RF circuits design

dc.contributor.guide	Jain, R. C. and Bhattacharyya, A. B.
dc.creator.researcher	Singh, Kirmender
dc.date.accessioned	2018-07-17T09:00:58Z
dc.date.available	2018-07-17T09:00:58Z
dc.date.awarded	07/06/2018
dc.date.completed	07/06/2018
dc.date.registered	09/07/2013
dc.description.abstract	included newline
dc.format.accompanyingmaterial	None
dc.identifier.uri	http://hdl.handle.net/10603/208513
dc.language	English
dc.publisher.institution	Department of Electronic & Communication
dc.publisher.place	Noida
dc.publisher.university	Jaypee Institute of Information Technology
dc.rights	university
dc.source.university	University
dc.subject.keyword	electronics
dc.subject.keyword	Internet of Things
dc.subject.keyword	MOS transistor
dc.subject.keyword	nanoscale CMOS
dc.subject.keyword	VLSI community
dc.title	Modeling deep submicron MOS transistor for ultra low-power analog and RF circuits design
dc.type.degree	Ph.D.