Analysis on high performance vedic multipliers and fast adders for fir filter implementation used in image processing applications

Abstract

The demand in the market for portable consumer electronics powered by batteries makes low power design as an important field of research There is an ongoing need to have energy efficient high speed circuits for less power with increasing density of transistors Low power requirement and smaller area design are the primary criteria in the fabrication of the Very large Scale Integration VLSI digital system The speed and the area are the different parameter issues increasing the speed result in a larger area. In today s era the infinite resolution goes on in the communication field and signal processing application. Digital Signal Processing (DSP) is applicable in newlineall engineering field The operation of discrete Fourier Transforms convolution digital filters etc requires a dedicated processor The performance of any processor is determined by the high speed adder and in particular by the adder employed in multiplier unit In the current scenario any DSP processors instruction cycle time is identified by the multiplication rate Many creative thoughts for multipliers were proposed to improve performance As the requirement for high speed processing has been expanding as an outcome of advancement in computer and signal processing newlineservices For any processing applications multipliers in association with adders were to be optimized With the innovation in technology the multiplier is designed to target any of these requirements satisfying increased speed less power consumption and regularity of layout for a compact area suitable for high performance VLSI implementation newline newline