Design experimentation and analysis of three phase multilevel inverter with reduced power quality issues
| dc.contributor.guide | Jovitha Jerome | en_US |
| dc.coverage.spatial | Power quality issues | en_US |
| dc.creator.researcher | Kumar Chinnaiyan V | en_US |
| dc.date.accessioned | 2013-08-05T06:00:11Z | |
| dc.date.available | 2013-08-05T06:00:11Z | |
| dc.date.awarded | en_US | |
| dc.date.completed | en_US | |
| dc.date.issued | 2013-08-05 | |
| dc.date.registered | 1, June 2011 | en_US |
| dc.description.abstract | Electrical supply system is a product and, like any other product, it should satisfy proper quality requirements. If electrical equipment is to operate correctly, it requires electrical energy to be supplied at a voltage that is within the specified range around the rated value. A significant part of the equipment in use today, especially electronic and computer devices requires good Power Quality (PQ) at its supply. Due to rapid changes in electrical technologies and environments, many problems have to be met with in electrical power distribution. The important power quality problem is harmonics, which is mainly produced due to large number of Adjustable Speed Drives (ASD), arc furnaces, personal computers and other nonlinear loads. The main objective of the proposed work is to develop a control technique from the conventional Sine Pulse Width Modulation (SPWM) for multilevel power electronic converter to reduce the power quality problems. In this work, the performance parameters of multilevel converters are analyzed with the developed prototype of a three phase five levels cascaded multilevel inverter with digital processor for improving power quality. In continuation of the work done in the past few decades on these multilevel inverters, the cascaded configuration has been chosen for hardware implementation. The next step is the selection of the suitable topology and levels for multilevel inverter. In the final step of the prototype development cycle, a complete five level cascaded multilevel inverter power circuit and the digital processor with suitable increment or decrement switches for variation of the amplitude, frequency and the driver circuits are connected and the pulses are tested with the cathode ray oscilloscopes. The results from the experimental setup show the output waveforms with reduced percentage of THD. It can be concluded that conventional drives with two level inverter can be replaced by multilevel inverter which results in the reduction of power loss. newline | en_US |
| dc.description.note | Appendix 1; pp.133-135 | en_US |
| dc.format.accompanyingmaterial | None | en_US |
| dc.format.dimensions | 23.5 cm x 15 cm | en_US |
| dc.format.extent | xxiv, 149 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10603/10306 | |
| dc.language | English | en_US |
| dc.publisher.institution | Faculty of Electrical and Electronics Engineering | en_US |
| dc.publisher.place | Chennai | en_US |
| dc.publisher.university | Anna University | en_US |
| dc.relation | 102 | en_US |
| dc.rights | university | en_US |
| dc.source.university | University | en_US |
| dc.subject.keyword | Multilevel inverter, power quality, adjustable speed drives, sine pulse width modulation, cascaded configuration, control technique | en_US |
| dc.title | Design experimentation and analysis of three phase multilevel inverter with reduced power quality issues | en_US |
| dc.title.alternative | en_US | |
| dc.type.degree | Ph.D. | en_US |
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