Investigations on the design of efficient vlsi architectures for multipliers

Abstract

Low power circuit design has now become an important subject of interest which is apparent from the advancements in the engineering and research domain In the past main focus was on operating frequency and device density not on power dissipation of the chip However as the scale of integration advances millions of transistors are being packed into a chip that leads to an increase in the processing capacity of chips and of power dissipation Earlier the major concerns among researchers and designers for designing integrated circuits were on area speed and cost while secondary importance was paid to power dissipation In recent years however this scenario has changed and now reducing power dissipation through improved circuit design techniques is an important research area The rapid increase in demand of portable devices requires low power designs It becomes an important area of research Besides speed and power dissipation are considered as one of the fundamental design objectives in Integrated Circuit IC design The parameters power area and speed always have trade off Hence high speed circuits consume larger area than low speed circuits A need for low power VLSI chips arises from Moores law Due to the increased market demand for the battery powered portable electronics low power VLSI chips are essential Battery life plays a vital role in many portable electronic markets newline