Analysis and Optimized Design of Low Power Semiconductor Memory Cell

Abstract

This work analyze various semiconductor memory cells (viz. SRAM and DRAM cells) and it will present their optimization with respect to power, retention margin, and area keeping other parameters as minimum as possible. Electronic storage devices are commonly considered to be the utmost important micro analog circuit portion of binary logic device scheme, such as calculator and and#956;-processor related uses varying from space stations to end user electronics. Solid state electronic storage processing units or non-erasable storage units are labeled as erasable random processing storage units. The digital information is either saved in random access memory by choosing the logic condition of a bi-stable one bit storage device such as F/F as in a Static Random Access Memory (SRAM), or by with a condenser as in Dynamic Random Access Memory (DRAM). In either case, information are processed and saved and it is read out as long as the voltage supply is functional and is nowhere to be found while the voltage supply is turned off; thus, it is termed erasable storage units, non-erasable storage device are competent to possess the statistics even after the voltage source is turned off. Non-erasable storage units are implemented in many areas such as in the PC, aeronautics, broadcastings, and end user electronics industries for software and program savings. Technology such as non-erasable RAM (neRAM) for implementation in devices that have need of negligible propagation delay, reprogrammable non-erasable storage, a grouping of erasable single IC including non-erasable buffer storage approaches is also delivered This research on electronic storage includes SRAMs and DRAMs and architectures unique to their use. For prototyping, plan and simulation of devices Synopsys HSPICE simulation tool will be used. For functional verification software Verilog, other SPICE tool may be used to analyze the performance of devices based on some parameters. newline