Optimization Techniques for Efficient VLSI Circuit Design

dc.contributor.guide	Balaji N
dc.coverage.spatial
dc.creator.researcher	Sujatha G
dc.date.accessioned	2025-01-13T07:56:38Z
dc.date.available	2025-01-13T07:56:38Z
dc.date.awarded	2022
dc.date.completed	2022
dc.date.registered	2012
dc.description.abstract	Attached newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	128pp.
dc.identifier.researcherid
dc.identifier.uri	http://hdl.handle.net/10603/614477
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Kukatpally
dc.publisher.university	Jawaharlal Nehru Technological University, Hyderabad
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Ant Colony Optimization
dc.subject.keyword	Bat Algorithm
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.subject.keyword	VLSI Circuit Design
dc.title	Optimization Techniques for Efficient VLSI Circuit Design
dc.title.alternative
dc.type.degree	Ph.D.