Image Compression Using DTCWT Hardware Accelerators for Plant Phenotyping Applications

Abstract

In this work, image compression-decompression algorithm for plant phenotyping newlineimages is developed that is based on shift invariant transform method such as Dual newlineTree Complex Wavelet Transform (DTCWT) and Set Partitioning in Hierarchical newlineTrees (SPIHT) algorithms. Companding algorithm is developed to capture the newlinedirectional information in the complex wavelet domain and is companded to generic newlinewavelet sub bands. Companded wavelet sub bands are encoded using SPIHT newlinealgorithm achieving compression of plant phenotype data. At the receiver, decoding is newlinecarried out using inverse Discrete Wavelet Transform (DWT) and inverse SPIHT to newlinereconstruct the image, thus reducing decoder computation complexity (Inverse newlineDTCWT is replaced using Inverse DWT). The complexity of decoder is less than two newlinetimes the complexity of inverse DTCWT based decompressor. The compressordecompressor model based on companding algorithm is evaluated for its newlineperformances considering plant phenotyping images. The proposed algorithm newlineoutperforms in terms of PSNR and MSE than the DWT based compression algorithm. newlineFor bpp 1 and above the PSNR is improved by a factor of 10% and for bpp less than 1 newlinethe PSNR is improved by a factor of 8%. With bpp of 1 the compression ratio is newline87.5% achieved and PSNR and MSE are higher than DWT based algorithm. newlineThe major challenge in use of DTCWT for image compression is decomposing the newlineinput image into DTCWT sub-bands. To accelerate the computation process, it is newlinerequired to design and develop customized architecture for DTCWT computation. newlineHigh speed DA logic is faster in terms of latency and throughput. The throughput is 5 newlineclocks between two successive outputs to be generated, and the first output is newlinegenerated after 15 clocks, demonstrating an improvement in latency. The memory bits newlinerequired for realizing high speed DA logic is 160 bits which is 84.375% improvement newlinecompared with direct DA method. The critical path is increased by addition of three newlineadder delay as compared with direct implementation. The advantage of the high-spe