Performance Optimization of Double Gate Mosfets for Nano Electronics Circuit Design Using Evolutionary Techniques

dc.contributor.guide	Kar, R. and Mandal, D. and De, B. P.
dc.coverage.spatial
dc.creator.researcher	Chowdhury, Dibyendu
dc.date.accessioned	2025-04-02T11:30:02Z
dc.date.available	2025-04-02T11:30:02Z
dc.date.awarded	2024
dc.date.completed	2023
dc.date.registered	2020
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent
dc.identifier.researcherid
dc.identifier.uri	http://hdl.handle.net/10603/631344
dc.language	English
dc.publisher.institution	Electronics and Communication Engineering
dc.publisher.place	Durgapur
dc.publisher.university	National Institute of Technology Durgapur
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Performance Optimization of Double Gate Mosfets for Nano Electronics Circuit Design Using Evolutionary Techniques
dc.title.alternative
dc.type.degree	Ph.D.