Certain hybrid on chip soft computing models for performance evaluation of SRAM cell in VLSI design applications

Abstract

Static Random Access Memory (SRAM) is a simple semiconductor memory device that develops a random access memory based storage that retains data in a static form. It is well known that static random access memory holds its data until the memory device has power. SRAM is the common memory type that is used in most of the Very Large Scale Integration (VLSI) designs. SRAM cell is volatile and in this memory data retention persists as long as the device gets power without any source for refresh or other means. When the power gets cuts, automatically the data is lost. In this case, the subsequent memory location that can be read or written is independent of the last access location. Static property of SRAM is based newlinefrom its use of certain sort of a feedback mechanism for maintaining the stored bit state. SRAM memory is employed at places where speed or low power is required. Less complicated design and its higher density makes it applicable in semiconductor memory devices where high capacity is needed and in case of working memory within computers. In this thesis work, new hybrid on-chip soft computing models are developed so as to evaluate the Data Retention Voltage (DRV) value which aids in minimizing the value of leakage current and as well hold the data in the SRAM cell. The developed models are validated for their randomness by carrying out statistical analysis and comparative analysis was made with the existing approaches to prove their effectiveness and reliable nature. The contributions made in this thesis are presented below. Firstly, a hybrid soft computing framework comprising a deep back propagation neural network which trains the fuzzy inference system to determine the performance metrics of 6T SRAM cell has been proposed newline newline