Certain investigations on the Performance improvement in virtual Secure circuit with dvanced Encryption standard for Cryptographic processor
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Abstract
Securing embedded systems not only require the security
newlineprotocols and cryptographic algorithms, but also the security
newlineimplementations. The data that are encrypted for secure transmission are
newlinethreatened by various attacks. One among them is a Side Channel Attack
newline(SCA) which breaks the cryptographic implementation within few hours
newlineresulting in a threat to embedded systems. This threat is overcome by an
newlinealgorithm independent Virtual Secure Circuit (VSC), which is used as a
newlinesoftware countermeasure to obviate the problem of SCA. Further the
newlinecomputation is processed by VSC with Advanced Encryption Standard
newline(AES) to analyse its performance in terms of delay and throughput in Field
newlineProgrammable Gate Array (FPGA) implementation. Though it thwarts the
newlineattacks, the parameters like delay and throughput are not as efficient as
newlineexpected in the implementation of VSC with AES. For improving the
newlineperformance of VSC with AES, a Fully Parallel Pipelined Architecture has
newlinebeen used to provide less delay and high throughput. The usage of resource
newlinesharing architecture and gate replacement methods in Mix-column techniques
newlinehelps to improve data reliability during transmission using TCP/IP protocol
newlinesuite and reduces the area utilisation and power consumption. To relatively
newlinereduce the power consumption a different method of SBox optimization is
newlineused in network.
newlineThis method is proposed with AES to provide the security and quality
newlineof transmission in various areas like hospitals and military application. The
newlineresults show performance improvement and optimisation of various
newlineparameters like Area Utilisation, Power consumption, Throughput, Delay and
newlineMaximum Frequency of Operation when compared with VSC with AES
newlinesystems.
newline