Efficient Lower Computational Complexity VLSI Architecture Using Machine Learning Algorithms

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dc.contributor.guideJain, Swapnil
dc.coverage.spatial
dc.creator.researcherYadav, Arpit Deepak
dc.date.accessioned2024-09-19T12:18:38Z
dc.date.available2024-09-19T12:18:38Z
dc.date.awarded2023
dc.date.completed2023
dc.date.registered
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/590334
dc.languageEnglish
dc.publisher.institutionShri Vaishnav Institute of Technology and Science
dc.publisher.placeIndore
dc.publisher.universityShri Vaishnav Vidyapeeth Vishwavidyalaya
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordComputational complexity
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Artificial Intelligence
dc.subject.keywordEngineering and Technology
dc.subject.keywordIntegrated circuits--Very large scale integration
dc.subject.keywordMachine learning
dc.titleEfficient Lower Computational Complexity VLSI Architecture Using Machine Learning Algorithms
dc.title.alternative
dc.type.degreePh.D.

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