Design and implementation of subnormal floating point soc for secured signal processing using pipeline interconnect

Abstract

Software level implementation, execution time variations of the equalsized inputs in a floating-point (FP) instruction are quantifiable that bring out the information of the executed data from a secured environment. These quantifiable timing variations are called as data timing channels (DTC). The exposed data state is captured and analysed by an adversary for retrieving the image pixels on a deep neural network (DNN) through multiplication timing channels (MTC). MTC is happened when normalized and subnormal FP numbers are taken for FP multiplication. Procedures used in normalization and denormalization have differed for normalized and subnormal numbers newlineused in FP arithmetic. Both procedures produce different amounts of delay in FP multiplication that results in MTC. In conventional CPU and GPU implementations, the combination of subnormal number and normalized number are not used in the FP addition and multiplication. newline newline