Certain investigations on low power versatile bit serial multiplier design for cryptoprocessor and channel coder

Abstract

The growing market of battery-powered electronic system newlinedemands low power microelectronic circuits design, that can be powered by newlinelightweight batteries with long battery time. There are three performance newlineparameters on which Very Large Scale Integration (VLSI) designers have to newlineoptimize the design i.e. area, speed and power. Most of the VLSI system newlinedesigners have focused on enhancing the speed and area of digital systems. newlineThe remarkable growth in the field of personal computing devices and newlinewireless communication industry considered power dissipation another newlinecritical design parameter. Yet, the high performance is still the major newlinecriterion for most digital systems, which may not be sacrificed to achieve newlinelower power dissipation.Multiplier is used for different applications and occupies a large newlinearea on Field Programmable Gate Array (FPGA). Multiplier is one of the key newlinehardware blocks in most of the digital and high speed systems. In fact the newlineoverall speed, area and power consumption of digital systems depends on newlineMultipliers, being the complex units. Multiplication in digital systems newlineexhibits a variety of requirements for speed, area, power consumption and newlineother specifications. The Multiplier design focuses on minimizing power newlinedissipation while still maintaining other parameters like area and maximum newlineclock frequency. To achieve significant power reduction in VLSI design, it is newlinenecessary to reduce the dynamic power dissipation of Multipliers. This is the newlinemajor part of total power dissipation. newline newline