Performance Evaluation of  on chip Interconnection Topologies for multi cores systems

dc.contributor.guide	Umar, M. Sarosh and Samad, Abdus
dc.coverage.spatial	225p.
dc.creator.researcher	Gautam, Savita
dc.date.accessioned	2024-05-06T10:22:41Z
dc.date.available	2024-05-06T10:22:41Z
dc.date.awarded	2023
dc.date.completed	2023
dc.date.registered
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	225p.
dc.identifier.uri	http://hdl.handle.net/10603/562994
dc.language	English
dc.publisher.institution	Department of Computer Engineering
dc.publisher.place	Aligarh
dc.publisher.university	Aligarh Muslim University
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Computer Science
dc.subject.keyword	Computer Science Hardware and Architecture
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Interconnects (Integrated circuit technology)
dc.title	Performance Evaluation of on chip Interconnection Topologies for multi cores systems
dc.title.alternative
dc.type.degree	Ph.D.