Adaptive efficient and prioritized approaches for integrated circuit testing

Abstract

The complexity of modern integrated circuits (ICs) presents newlinemany challenges when testing them. These challenges include higher costs newlineand more extended testing times, which can significantly impact the newlineefficiency and cost-effectiveness of IC manufacturing. It is, therefore, newlineessential to find innovative solutions to reconcile the conflicting demands of newlinerigorous IC testing and the constraints of available resources, such as time newlineand budget. One of the main challenges associated with testing ICs is the newlineproliferation of test patterns. This is a direct result of the increasing newlinecomplexity of ICs, which requires many test patterns to ensure newlinecomprehensive testing. However, this leads to two interconnected problems: newlinelonger testing times and higher testing costs. Traditional testing methods that newlineinvolve applying each test pattern sequentially are no longer sustainable as newlineICs become more complex. Exhaustive testing can account for a significant newlineproportion of the overall project cost, ranging from 30% to 50%. newlineTo address these challenges, researchers have explored the newlinepotential of adaptive testing (AT) and test pattern reordering as innovative newlinesolutions. These approaches prioritize the most effective test patterns, newlineenhancing error detection rates while minimizing resource-intensive testing. newlineWithin the realm of AT, two primary strategies are employed: the selection newlineof optimal test patterns and the rearrangement of the test pattern order. These newlinestrategies expedite the identification of faulty ICs, effectively reducing test newlinetimes and costs. newline