Design of Performance Centric 2D and 3D Network on Chips

Abstract

The shrinking fabrication geometry of Integrated Circuits (ICs) has paved the newline way for emerging today s System-on-Chips (SoCs). The decreasing device feature newline size has made it possible for an IC chip to subsume billions of transistors nowa newlinedays. The demand for execution concurrency impels the multicore infrastructure newline to replace a large superscalar processing engine to enable thread-level parallelism. newline Gradually, replacing a monolithic cache memory, the use of a multilevel cache hi newlineerarchy is commenced in multicore SoCs. Hierarchical cache design necessitates newline part of the memory used in shared mode. Modularized chip architectures open up newline a new dimension of design challenges where intercommunication among the var newlineious components, like processing cores and cache banks, becomes indispensable. newline Eventually, the shared cache memory used by multiple processing cores through newline a bus-based interconnect becomes the principal constraint for system scalability. newline The growing system size brings complexity to the bus interconnect. As a manifes newlinetation, critical arbitration timing, high communication latency, and propagation newline delay through the long wires create coherence problems in the shared cache sys newlinetem of a multicore SoC. Inevitably, the Network-on-Chip (NoC) interconnect has newline evolved as the modern communication backbone for multicore SoCs. newline Employing a network of tiny routers and channels inside a chip facilitates simulta newlineneous communication for several components (like processing cores, cache blocks, newline etc.). As a result, unlike the bus-based data transfer, the blocking time is signifi newlinecantly reduced for the communicating nodes in the case of NoC. In consequence, newline the communication latency using a NoC is eminently decreased. An on-chip net newlinework eliminates the delay induced by the complex arbitration processes in the bus newline vii newlineviii newline interconnects, compartmentalizing the communication infrastructure into several newline concurrent units called routers or switches. Furthermore, the various synchro newlinenization issues due to