Detection of Hardware Trojans in ICs Based on Logic Testing and Machine Learning

dc.contributor.guideRoy Surajit Kumar
dc.coverage.spatial
dc.creator.researcherDhar, Tapobrata
dc.date.accessioned2026-02-03T11:49:56Z
dc.date.available2026-02-03T11:49:56Z
dc.date.awarded2025
dc.date.completed2025
dc.date.registered2018
dc.description.abstractMalicious modifications called hardware Trojan horses can be introduced within the circuit the fabless manufacturing process. This thesis explores reduction of rarity of signal transition within the circuits through design for testing methods todetect Trojans. 2-to-1 multiplexers and tri-state buffers paired with scan-chain registers are utilised to increase the probability of signal transitions in all the nets of the circuit. This thesis delves into reduction in overhead for design-for-security additions to detect Trojan nets. Novel circuit parameters paired with established testability measures are utilised to determine appropriate threshold of signal transitions through unsupervised clustering. Transitions in signals of the nets throughout the circuit are bolstered with the tri-state buffers beyond the determined threshold. This thesis presents a golden-model free unsupervised static analysis method for detecting malicious nets. Established and newly introduced gate-level Trojan features are extracted and feature subsets are obtained pertaining to nature of combinational and sequential Trojans. Heuristic localisation process is used over unsupervised classifier results to identify malicious nets. This thesis also analyses effective threshold consideration for probabilistic classifier designed for supervised static analysis technique to detect the presence of Trojans. Effective features are selected using their feature importance values and variance threshold. Threshold values of the probabilistic classifier are determined through analysis of receiver operating characteristic and precision-recall curves. This dissertation proposes a test vector generation procedure that focuses on activating payload nets of Trojans. Various features of payload are extracted from gate-level Trust-Hub circuits to train neural network classifier to generate weighted random vectors. Gaussian Mixture Model is used on these vectors to generate test vector subset. newline
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions
dc.format.extent176
dc.identifier.researcherid0000-0002-4848-5524
dc.identifier.urihttp://hdl.handle.net/10603/692136
dc.languageEnglish
dc.publisher.institutionDepartment of Information Technology
dc.publisher.placeShibpur
dc.publisher.universityIndian Institute of Engineering Science and Technology, Shibpur
dc.relation
dc.rightsself
dc.source.universityUniversity
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Hardware and Architecture
dc.subject.keywordEngineering and Technology
dc.titleDetection of Hardware Trojans in ICs Based on Logic Testing and Machine Learning
dc.title.alternative
dc.type.degreePh.D.

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