Soft error performance of junction and junctionless silicon nanotube fet based sram and inverter chain

Abstract

The youngest candidate in the multi-gate FET family, Silicon nano newlinetube (SiNT FET), is studied for its single event/soft error performance. Both newlinejunction and junctionless devices are considered in this thesis. Mixed mode newlinenumerical device simulations are used to carry out the work. The work is done newlineat two levels (i) device level and (ii) circuit level. newlineThe device level single event effect is carried by analyzing the single newlineevent transient current pulses. The collected charge due to the single event newlinestrike/radiation strike is calculated from the transients, and is used a figure of newlinemerit to analyze the performance. Based on the collected charge, it has been newlineconcluded that the junctionless SiNT is more vulnerable to single event strike newlinecompared to junction-based SiNT. The studies also reveal that an insensitive newlinelocation, for example source region, could become sensitive location newlinedepending upon the incident angle of the radiation. Similarly, a sensitive newlineregion could become less sensitive to radiation in some range of the incident newlineangle. Typically the particle strikes/enter the device and comes out. This newlineentry-exit process is more interesting in the tubular channel. Since SiNT FET newlinehas tubular channel the particle may escape through the center portion of the newlinetube without disturbing the other side of the tube, for some angles. A simple newlinemodel is proposed to find out these angles, known as critical angles. newlineAt the circuit level, two 6T SRAMs, (i) a minimum sized 6T SRAM newlineusing junction-based SiNT FET devices (ii) a minimum sized 6T SRAM newlineusing junctionless SiNT FET devices, are designed and compared for their newlinesoft error performance. newline newline