Analysis and Implementation of Cascaded Multilevel Inverter Topologies with Reduced Number of Components

dc.contributor.guide	Meikandasivam .S
dc.coverage.spatial
dc.creator.researcher	Dhanamjayulu.C
dc.date.accessioned	2018-12-24T06:17:00Z
dc.date.available	2018-12-24T06:17:00Z
dc.date.awarded	21/09/2018
dc.date.completed	2018
dc.date.registered	23/03/2013
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent	I-XII,1-168
dc.identifier.uri	http://hdl.handle.net/10603/224334
dc.language	English
dc.publisher.institution	School of Electrical Engineering
dc.publisher.place	Vellore
dc.publisher.university	VIT University
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Asymmetric Multilevel Inverter (AMLI)
dc.subject.keyword	Engineering and Technology,Engineering,Engineering Electrical and Electronic
dc.subject.keyword	High output voltage levels
dc.subject.keyword	Multilevel Inverter (MLI)
dc.title	Analysis and Implementation of Cascaded Multilevel Inverter Topologies with Reduced Number of Components
dc.title.alternative
dc.type.degree	Ph.D.