Parasitic gate capacitance and sourcedrain series resistance modeling of nanosheet and forksheet fets

dc.contributor.guide	Dey, Rik and Sahay, Shubham
dc.coverage.spatial
dc.creator.researcher	Sharma, Sanjay
dc.date.accessioned	2025-10-17T09:30:19Z
dc.date.available	2025-10-17T09:30:19Z
dc.date.awarded	2025
dc.date.completed	2025
dc.date.registered	2017
dc.description.abstract	Abstract file attached separately.
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent	xxv, 133p
dc.identifier.researcherid
dc.identifier.uri	http://hdl.handle.net/10603/668985
dc.language	English
dc.publisher.institution	ELECTRICAL ENGINEERING
dc.publisher.place	Kanpur
dc.publisher.university	Indian Institute of Technology Kanpur
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Parasitic gate capacitance and sourcedrain series resistance modeling of nanosheet and forksheet fets
dc.title.alternative
dc.type.degree	Ph.D.