Certain investigations on high performance cordic based efficient VLSI architectures for fast fourier transform

Abstract

Fast Fourier Transform (FFT) algorithms are the efficient methods to compute Discrete Fourier Transform (DFT) with reduced computations. FFT architectures consume high power and occupy more area. Therefore, efficient FFT architecture is required for real time application. In FFT architectures, butterfly operation is the most computationally demanding stage. Conventional butterfly unit consists of complex adders and complex multipliers. Complex multipliers perform the twiddle factor multiplication. They occupy large area with long latency and consume considerable power. So, the implementation of low-power high speed complex multiplier is a challenging task in low power FFT architecture design. Therefore, in this work, the twiddle factor multiplication is performed by Coordinate Rotation newlineDigital Computer (CORDIC) algorithm. Due to this, the complex multiplier is newlinecompletely removed from FFT architecture. CORDIC is an iterative algorithm that rotates the two-dimensional vectors in linear, circular and hyperbolic coordinate systems by performing a micro-rotation in each iteration. In addition to the rotation, the vector is scaled in each iteration. CORDIC algorithm performs twiddle factor multiplication using only adders and shifters. Due to this, the complexity of FFT newlinearchitectures is reduced. In CORDIC-based FFT processor, the memory required for storing twiddle factor is also reduced. However, CORDIC algorithm has slow computational speed due to its iterative structure and the speed of CORDIC operation is limited by the number of iterations, which are equal to the internal word-length. For example, at least N rotations must be performed in order to achieve newlineN-bits of accuracy. newline newline