Performance Analysis of Binary Adders and Multipliers for Signal Processing applications

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dc.contributor.guideRakesh Kumar Karn
dc.coverage.spatial
dc.creator.researcherRadhakrishnan S
dc.date.accessioned2024-01-17T09:04:00Z
dc.date.available2024-01-17T09:04:00Z
dc.date.awarded2023
dc.date.completed2023
dc.date.registered2014
dc.description.abstractAbstract Included newline
dc.description.notereferences 95-102p Appendix 103-105p
dc.format.accompanyingmaterialNone
dc.format.dimensions28 cm
dc.format.extentxv, 105p
dc.identifier.urihttp://hdl.handle.net/10603/540198
dc.languageEnglish
dc.publisher.institutionSchool of Electrical and Electronics Engineering
dc.publisher.placeThanjavur
dc.publisher.universitySASTRA University
dc.relation93
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titlePerformance Analysis of Binary Adders and Multipliers for Signal Processing applications
dc.title.alternative
dc.type.degreePh.D.

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