Design and implementation of resource efficient bitstream compression techniques for xilinx fpga family based high speed embedded systems

Abstract

Field Programmable Gate Arrays (FPGA) is applied to the recent applications, such as medical electronics, scientific instruments, video and image processing, and security system. The FPGA requires huge quantity of storage space. To convince this storage needs, the modern FPGA strategies are essential with the aim of large memory with decent yield cost. To moderate these troubles, the compression method is chosen to resize the stream of bits that is appropriate for FPGA configuration. This new compression method is presented to get better compression ratio and bit saving gain. The proposed code compression technique is an integrated scheme that merges Run Length Encoding (RLE) and Golomb coding. The present RG-1 and RG-2 restrain the restriction of mutually RLE and Golomb coding methods. The present approach applies a multi-view thought that the resources contribute 1 s count up, transitions count up, and dimension of compressed bits. The RG-1 and RG-2, obtained result shows considerable improvement in compression rate. Moreover, comparing compression schemes such as RLE and Golomb, relative result shows that the parameter Compression Ratio of former scheme is reduced to 9% and 5% on applying RG-1 and RG-2 and later scheme to 7% and 2% respectively. The RG-1 method operates with the well-known value of remaining codes and RG-2 method takes the least quantity of power. Two effective compression methods are termed as Separated Split LUT (SSL) and Bit masked Separated Split LUT (BSSL) to offer high compression rate and bit saving rate. This moderates the issues in the DCCDictionary based code compression that is the most regularly applied bitstream compression method. In this method, the bit-streams are does not maintained in the dictionary create it as an uncompressed configure that requirements huge memory range. The proposed compression algorithms are implicit in Verilog or VHDL, and synthesized by Xilinx ISE 9.1i and implemented in Spartan-3E Field Programmable Gate Array (FPGA). The planned compression methods