Optimization of power management in devices and circuit technology

Abstract

CMOS technology in VLSI has led to compact and portable devices where Size reduction has played more important role At the same time more concentration is needed to optimize the power dissipation and speed of the circuit So an effective low power technique in VLSI is required that has less power dissipation than conventional CMOS which can be carried out by means of adiabatic technique Many adiabatic technique like ECRL TSEL introduced by modifying the circuit to reduce the area power and speed Power dissipation in ICs is closely linked to the choice of technology circuit design and also the scale of integration Even after choosing a technology VLSI designers need to minimize the power dissipation while meeting other design objectives such as speed chip area device cost and reliability Dissipation of dynamic power has been a major criteria for circuit designers Several circuit technologies have been presented for decreasing dynamic power such as sub threshold logic multi threshold technology and adiabatic logic circuit From different types of adiabatic logic identifying suitable circuit technology super conservative reversible logic SCRL 5 gate is simulated for bitwise swapping Less power consumption is achieved by super conservative reversible logic in QCA and for split charge recovery logic in johnson counter Quantum devices analyzed to find out less power consumption device newline