Ultra low power digital VLSI Design Design Implementation and Analysis of Low Power High Speed SRAM

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dc.contributor.guideYOGESH CHANDRA SHARMA, K J RANGRA, VAIBHAV NEEMA
dc.coverage.spatial
dc.creator.researcherNIDHI TIWARI
dc.date.accessioned2018-07-13T05:01:01Z
dc.date.available2018-07-13T05:01:01Z
dc.date.awarded7/7/2018
dc.date.completed2018
dc.date.registered23/12/2014
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/207858
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication
dc.publisher.placeJaipur
dc.publisher.universityVivekananda Global University
dc.relation
dc.rightsself
dc.source.universityUniversity
dc.titleUltra low power digital VLSI Design Design Implementation and Analysis of Low Power High Speed SRAM
dc.title.alternativeUltra-low power digital VLSI Design: Design, Implementation and Analysis of Low Power High-Speed SRAM
dc.type.degreePh.D.

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