Physical modeling of latch UP characteristics in VLSI CMOS devices

dc.contributor.guide	Zarabi, M. J. and Bhattacharyya, A. B.
dc.coverage.spatial	Centre for Applied Research in Electronices
dc.creator.researcher	Bandyopadhyay, A.
dc.date.accessioned	2024-12-04T05:38:27Z
dc.date.available	2024-12-04T05:38:27Z
dc.date.awarded	1990
dc.date.completed	1990
dc.date.registered
dc.description.abstract	Abstract available newline
dc.description.note	NA
dc.format.accompanyingmaterial	DVD
dc.format.dimensions	NA
dc.format.extent	NA
dc.identifier.uri	http://hdl.handle.net/10603/604616
dc.language	English
dc.publisher.institution	Centre for Applied Research in Electronics
dc.publisher.place	Delhi
dc.publisher.university	Indian Institute of Technology Delhi
dc.relation	TH1826
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Physical modeling of latch UP characteristics in VLSI CMOS devices
dc.title.alternative	NA
dc.type.degree	Ph.D.