Low power test data compression architecture using innovative algorithm

dc.contributor.guide	Jayanthi, K B
dc.coverage.spatial	Information and Communication Engineering
dc.creator.researcher	S, Neelukumari K
dc.date.accessioned	2017-11-16T04:59:00Z
dc.date.available	2017-11-16T04:59:00Z
dc.date.awarded	n.d.
dc.date.completed	2016
dc.date.registered	n.d.
dc.description.abstract	Abstract available
dc.description.note	Data not available
dc.format.accompanyingmaterial	None
dc.format.dimensions	31cm.
dc.format.extent	xvii, 120p.
dc.identifier.uri	http://hdl.handle.net/10603/180947
dc.language	English US
dc.publisher.institution	Faculty of Information and Communication Engineering
dc.publisher.place	Chennai
dc.publisher.university	Anna University
dc.relation	111-119
dc.rights	university
dc.source.university	University
dc.subject.keyword	Architecture
dc.subject.keyword	Data
dc.subject.keyword	Innovative
dc.subject.keyword	Low
dc.subject.keyword	Power
dc.title	Low power test data compression architecture using innovative algorithm
dc.title.alternative
dc.type.degree	Ph.D.