Study and analysis of matrix multiplication using floating point number on a reconfigurable device

Abstract

In the present scenario the rapid growth of wireless communication multimedia applications robotics and graphics increases the demand for resource efficient high throughput and low power digital signal processing DSPsystems Floating point matrix multiplication is the most widely used fundamental processing element in almost all DSP systems ranging from audio video signal processing to wireless sensor networks Hardware implementation of Floating point matrix multiplication requires a huge number of arithmetic operations that affect the speed and consumes more area and power Pipelining and parallel processing are the two methods used in the DSP systems to reduce the dynamic power consumption Demand for high performance processing element with less area and low power increases in various scientific computing applications Consequently the number of adders and multipliers used in the design of floating point unit also increases gradually The adders and multipliers are the most area delay and power consuming data path elements in the processing unit The arithmetic level reduction of delay power and area in the processing element is done by choosing appropriate adders and multipliers The proposed design of floating point matrix multiplication is based on rank 1 update algorithm using pipelined architecture The performance of the algorithm is determined by the performance of the multiplier unit. newline