Resource contention aware performance and power optimization in chip multiprocessors

dc.contributor.guide	Balakrishnan, M and Anshul Kumar
dc.coverage.spatial	Computer Science and Engineering
dc.creator.researcher	Abera, Solomon
dc.date.accessioned	2022-12-06T05:01:48Z
dc.date.available	2022-12-06T05:01:48Z
dc.date.awarded	2021
dc.date.completed	2021
dc.date.registered
dc.description.abstract	Abstract Available
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent
dc.identifier.uri	http://hdl.handle.net/10603/421781
dc.language	English
dc.publisher.institution	Department of Computer Science and Engineering
dc.publisher.place	Delhi
dc.publisher.university	Indian Institute of Technology Delhi
dc.relation	TH-6514
dc.rights	university
dc.source.university	University
dc.subject.keyword	Computer Science
dc.subject.keyword	Computer Science Software Engineering
dc.subject.keyword	Engineering and Technology
dc.title	Resource contention aware performance and power optimization in chip multiprocessors
dc.title.alternative	Na
dc.type.degree	Ph.D.