Performance enhancement of 3D cylindrical gate all around tunnel FET and its applications for ultra low power cross coupled voltage doubler circuit design

dc.contributor.guide	Vishvakarma, Santosh Kumar
dc.coverage.spatial
dc.creator.researcher	Beohar, Ankur
dc.date.accessioned	2023-01-12T11:46:39Z
dc.date.available	2023-01-12T11:46:39Z
dc.date.awarded	2019
dc.date.completed	2019
dc.date.registered	2014
dc.description.abstract	Available newline
dc.description.note	TH170
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent	116p.
dc.identifier.uri	http://hdl.handle.net/10603/444244
dc.language	English
dc.publisher.institution	Department of Electrical Engineering
dc.publisher.place	Indore
dc.publisher.university	Indian Institute of Technology Indore
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Performance enhancement of 3D cylindrical gate all around tunnel FET and its applications for ultra low power cross coupled voltage doubler circuit design
dc.title.alternative
dc.type.degree	Ph.D.