Certain investigations on low power by passing 2d multipliers design using different types of full adder logics

Abstract

Very Large Scale Integrated (VLSI) circuit technology is one of the fastest growing technologies for a varied range of innovative devices and systems that have been changing the world today. Major concerns of VLSI designer are area, performance, cost and reliability of the system. System with high power dissipation generally results in minimal battery life, unintended operation and IC damage. Low power generally results in least power supplies, inexpensive batteries and reliable system. Multiplier circuit is the most important component of more of the digital signal processors. Hence, the demand for multiplier performance growth is essential in the present scenario. Multipliers are the chief source of power dissipation in modern VLSI system. Minimize the energy dissipation of multipliers is inevitable to handle the entire power budget of a wide range of digital circuits. Multiplier circuit performance in terms of power, area and speed can be improved by minimizing the transistors used in Full Adder (FA) circuit. The main objective of the research work is to incorporate the CMOS technology in the 2D bypassing multiplier design in order to minimize the consumption of power, power delay product and the space occupancy (area).In this first research method, low power and high-performance two-dimensional bypassing multipliers are exploited by using 15T modified incremental adder. In order to achieve better power reduction, 3T XOR and 2T multiplexer gate are utilized instead of 8T XOR gate and 6T multiplexer gate. Reduction of transistors minimizes area, power, critical path delay and improves the speed of circuit newline