Effects of Process variation on the performance parameters of VLSI interconnects

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dc.contributor.guideKaushik, B.K.;Singh , Raghuviren_US
dc.coverage.spatialen_US
dc.creator.researcherK.G Vermaen_US
dc.date.accessioned2015-05-05T05:24:31Z
dc.date.available2015-05-05T05:24:31Z
dc.date.awarded26/05/2012en_US
dc.date.completed20/08/2011en_US
dc.date.issued2015-05-05
dc.date.registered07/06/2008en_US
dc.description.abstractnewlineen_US
dc.description.noteattacheden_US
dc.format.accompanyingmaterialNoneen_US
dc.format.dimensionsen_US
dc.format.extenten_US
dc.identifier.urihttp://hdl.handle.net/10603/40032
dc.languageEnglishen_US
dc.publisher.institutionFaculty of Engineering and Technologyen_US
dc.publisher.placeMeeruten_US
dc.publisher.universityShobhit Universityen_US
dc.relationen_US
dc.rightsuniversityen_US
dc.source.universityUniversityen_US
dc.subject.keywordInterlayer capacitance, Chemical mechanical planarization, Optical proximity correctionen_US
dc.titleEffects of Process variation on the performance parameters of VLSI interconnectsen_US
dc.title.alternativeen_US
dc.type.degreePh.D.en_US

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