Architecture Formulation of Multi Dimensional Clustering Algorithms for Image Analysis

dc.contributor.guideBASAVARAJ, L
dc.coverage.spatial
dc.creator.researcherANURADHA, M G
dc.date.accessioned2023-02-18T10:03:22Z
dc.date.available2023-02-18T10:03:22Z
dc.date.awarded2022
dc.date.completed2021
dc.date.registered2013
dc.description.abstractThe real world task such as audio and visual processing is carried out easily by the human brain. These functions are called Cognitive functions which need to be carried out artificially by a machine from the data samples collected. Clustering is one such machine learning cognitive function developed to realize the learning operations. newlineThe computations in the clustering algorithm are complex and iterative and hence implementation cost in terms of speed of the algorithm is a critical issue. To increase the performance of the learning algorithms, attempts are being made to implement these clustering algorithms using hardware like Graphic processing unit, Field programmable gate array and VLSI circuits as application specific Integrated circuits. There is a challenge on the hardware implementations as there is a requirement of high speed operation with low hardware resources and low power requirement.In the thesis, various architectures of these clustering algorithms are proposed and implemented on Virtex 6 FPGA which process or cluster the image at higher rate.The hardware architectures are built for On-line clustering algorithm, K-Means clustering algorithm and Mean shift algorithm. newlineThe first algorithm implemented is On-line clustering algorithm which is a two pass clustering algorithm. To avoid the memory overhead to store the input image, the moving average method calculating the mean of the cluster is used where the input data can be discarded after computation of the centroids. To speed up the clustering process, architecture for divider is proposed which can perform the division operation of the data varied up to 8 dimensions in one clock cycle. Due to pipeline approach, the throughput of one clock cycle is achieved. The architecture is implemented in Virtex 6 FPGA and the synthesized design shows that the maximum frequency is 45.9MHz and process 350 image frames in a second if the size of the image is 256X256 pixels. newline
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions
dc.format.extentAll Pages
dc.identifier.urihttp://hdl.handle.net/10603/462691
dc.languageEnglish
dc.publisher.institutionATME College of Engineering Mysuru
dc.publisher.placeBelagavi
dc.publisher.universityVisvesvaraya Technological University, Belagavi
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleArchitecture Formulation of Multi Dimensional Clustering Algorithms for Image Analysis
dc.title.alternative
dc.type.degreePh.D.

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