Analysis Mitigation of Leakage Mechanisms in Planar MOS Devices and Incorporation of Performance Improvement Methodologies

dc.contributor.guide	Aditya Sankar Medury
dc.coverage.spatial
dc.creator.researcher	Harshit Kansal
dc.date.accessioned	2024-05-20T08:31:51Z
dc.date.available	2024-05-20T08:31:51Z
dc.date.awarded	2023
dc.date.completed	2022
dc.date.registered	2016
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent	xxviii,130
dc.identifier.uri	http://hdl.handle.net/10603/564660
dc.language	English
dc.publisher.institution	Electrical Engineering and Computer Science
dc.publisher.place	Bhopal
dc.publisher.university	Indian Institute of Science Education and Research (IISER) Bhopal
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Analysis Mitigation of Leakage Mechanisms in Planar MOS Devices and Incorporation of Performance Improvement Methodologies
dc.title.alternative
dc.type.degree	Ph.D.