Design and Development of Simplified Logical Method for Balancing the Capacitor Voltage in Modular Multilevel Converter

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dc.contributor.guideSaravanan, K
dc.coverage.spatial
dc.creator.researcherHidayathullah, M
dc.date.accessioned2022-12-09T06:38:25Z
dc.date.available2022-12-09T06:38:25Z
dc.date.awarded2022
dc.date.completed2022
dc.date.registered
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/423420
dc.languageEnglish
dc.publisher.institutionDepartment of Electrical and Electronics Engineering
dc.publisher.placeKattankulathur
dc.publisher.universitySRM Institute of Science and Technology
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleDesign and Development of Simplified Logical Method for Balancing the Capacitor Voltage in Modular Multilevel Converter
dc.title.alternative
dc.type.degreePh.D.

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