Design space exploration of capacitor voltage balancing and modulation methods for modular multilevel converters

Abstract

Modular multilevel converter (MMC) topology has attracted much research encouragement newlinein medium voltage and high power applications. The modular structure newlineof MMC offers manifold advantages such as scalability, modularity, and excellent newlineoutput performance at a lower switching frequency. However, there are issues with newlinethe submodule (SM) capacitor voltage balancing in MMCs. The insertion and bypass newlineoperation of SMs need to be carried out such that the SM capacitor voltages remain newlineclose to their nominal values. The average power transfer through each SM capacitor newlineshould be zero, which is necessary to maintain the average SM capacitor voltage newlineconstant. However, the instantaneous power of each SM capacitor comprises oscillations newlineat a frequency, which is typically a multiple of the fundamental frequency. newlineThe oscillations lead to variations in the SM capacitors voltage, which is the major newlinedrawback of MMC topology. In order to ensure reliable and effective operation of the newlineMMC, capacitor voltage balancing and modulation techniques, as well as the need for newlinecomparatively low switching frequencies, present a particular set of challenges. This newlineresearch aims to explore the methods of capacitor voltage balancing and modulation newlinestrategies for MMC with less hardware and computational overhead. newlineThe work proposes a voltage balancing scheme for the MMC based on capacitor newlinecharge variation in each fundamental cycle. An in-depth theoretical analysis of newlinestored charge variation for the concept is described. A new hybrid PWM sequence is newlineproposed based on rotation strategy to achieve capacitor voltage balancing without newlinesensing the capacitor voltages or arm currents. This approach leads to a fixed number newlineof SMs inserted at any instant of time, which is equal to N. This reduces the hardware, newlinesoftware burden, and overall cost of the design implementation. newline