Performance evaluation of nonvolatile magnetic memories for low power computing systems and ai applications

Abstract

The continuous downscaling of CMOS technology has reached a point where newlineleakage power, scalability, and performance limitations have become newlinesignificant challenges. This has prompted a paradigm shift in research focus newlinetoward More than Moore approaches, emphasizing unconventional devices newlinethat can either supplement or replace traditional CMOS technologies. Among newlinethese emerging solutions, non-volatile memory (NVM) technologies have newlineshown significant promise due to their non-volatility, high density, ultra-low newlinepower consumption, and scalability. newlineThis thesis investigates the potential of NVM technologies in addressing the newlinepower consumption challenges of on-chip caches within modern computing newlinedevices. By focusing on the memory hierarchy of processor chips, this research newlineestablishes a comprehensive simulation framework to evaluate the newlineperformance and energy efficiency of NVM caches compared to conventional newlineSRAM. The study spans memory array-level evaluations, architectural newlineanalyses, and system-level benchmarking, offering valuable insights into the newlinesuitability of various NVM technologies, including SOT-MRAM, Spin- newlineTransfer Torque MRAM (STT-MRAM), Voltage-Controlled Magnetic newlineAnisotropy (VCMA) MRAM, STT-Aggressive (STT-A) MRAM, and newlineResistive RAM (RRAM). newlineThe findings highlight the superiority of SOT-MRAM for cache sizes larger newlinethan 128 KB, with significant energy savings of up to 74% and leakage power newlinereductions exceeding 99% compared to SRAM. SOT-MRAM and VCMAMRAM newlineexhibit superior speeds. Full-system evaluation determines that SOTMRAM newlineis gt30% more energy efficient and achieves ~40% lower EDP than newlineSRAM for a 32 KB L1 and 512 KB L2 in a 4-core ARM cluster. Architectural newlineinnovations, such as power gating and reduced-tag cache implementations, newlinewere experimented with. Power gating in NVM L2 caches can be achieved for newline~85% of the runtime, leading to a further reduction of 18% in total power newlineconsumption. The reduced-tag technique improves dynamic energy by ~10% newlinefor SOT-MRAM and write performance by 15% for STT-MRAM