Optimized Architecture of Lightweight Block Cipher for Secured Data Transmission

Abstract

The internet era has led to a surge in network-based technologies across various industries. In such a landscape, the ubiquity of intelligent devices underscores the importance of secure data communication. Developing innovative solutions to tackle critical aspects such as data transfer speed, response time, hardware utilization, and data security is necessary. newlineData security, a significant concern, is addressed by cryptographic algorithms, commonly referred to as ciphers. These algorithms ensure data confidentiality, integrity, and authenticity during communication. They are the backbone of secure data transmission in our increasingly connected world. However, integrating cryptographic processing in data transmission introduces issues, including the need for additional hardware, increased latency, and decreased throughput. These issues become more noticeable in tiny smart devices, where resources are limited, and efficiency is paramount. newlineThis research optimizes lightweight ciphers, specifically the PRESENT and GIFT ciphers, crucial for secure data transfer applications in tiny smart devices. These ciphers were chosen for their compact size, energy efficiency, and suitability for low-power consumption devices. newlineThe novelty of this research lies in the optimized cipher architectures that enhance throughput through three distinct optimizations: modifications to data path size, and the incorporation of newlinex newlineBit Slice Parallel Resource Reutilization (BPRR) PRESENT, High Throughput Pipeline (HTP) GIFT, and sub-pipeline HTP-GIFT approaches. These proposed architectures demonstrate significant improvements in throughput and latency, making them a novel contribution to secure data transfer in tiny smart devices. newlineThe proposed BPRR-PRESENT architecture, designed and simulated using XC7Z030FBG676-2 Xilinx Vivado software. demonstrates an increase in throughput to 85.54% and a reduction in latency to 46%. Xilinx Vivado, a design software that reduces compile times and is widely used in the industry, was chosen for this purpose.