Design And Analysis Of High Throughput And Low Power Hybrid Recursive Systematic Convolutional Encoder And Decoder Technique

Abstract

The main aim of the research work focuses on the different newlineresearch work carried out towards the design and development of newlineencoder and decoder techniques for recent communication technologies. newlineInitially, it started with different type of coding techniques and followed newlineby encoding process for all type of communication technologies. newlineFinally, performance analysis of different encoding techniques is shown newlineto prove the importance of the method used in 6G communication. newlineSo the first approach is to propose a convolutional encoder newlinewhich consists of both Recursive Systematic Convolutional (RSC) newlineEncoder and Adaptive Variable-Rate Convolutional (AVRC) encoder. newlineAdaptive Variable-Rate Convolutional encoder improves the bit error newlinerate performance and is more suitable for a power-constrained wireless newlinesystem to transfer the data. Recursive Systematic Convolutional encoder newlinealso reduces the bit error rate and improves the throughput by newlineemploying the trellis termination strategy. Here, AVRC encoder newlineultimately acquires the channel state information and feeds the data into newlinea fixed rate convolutional encoder and rate adaptor followed by a buffer newlinedevice. A hybrid encoder combines the AVRC encoder and RSC newlineencoder output serially and parallel, producing the solid encoded data newlinefor the modulator in the communication system. A modified turbo code newlineis also obtained by placing interleaver between the two encoder units newlineand building the stronger code word for the system. newlineIn the second approach, the finite state machine based trellis newlineencoding is proposed in the convolutional encoder for minimizing the newlineix newlinesystem complexity. Moreover, the folding transformation is proposed in newlinethe Viterbi decoder for minimizing the number of stages processed newlinewhile decoding the encoded data bits. The main objective of this newlineproposed system is that the reconstruction of original data bits with less newlineerrors. The performance of the proposed system is analyzed in terms of newlinenumber of slice LUT, number of slice register, BRAM, delay and failure newlinerate.